JPS6033437U - リ−ド無しチップキャリヤ構造 - Google Patents
リ−ド無しチップキャリヤ構造Info
- Publication number
- JPS6033437U JPS6033437U JP12332483U JP12332483U JPS6033437U JP S6033437 U JPS6033437 U JP S6033437U JP 12332483 U JP12332483 U JP 12332483U JP 12332483 U JP12332483 U JP 12332483U JP S6033437 U JPS6033437 U JP S6033437U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- chip carrier
- carrier structure
- leadless chip
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12332483U JPS6033437U (ja) | 1983-08-10 | 1983-08-10 | リ−ド無しチップキャリヤ構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12332483U JPS6033437U (ja) | 1983-08-10 | 1983-08-10 | リ−ド無しチップキャリヤ構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6033437U true JPS6033437U (ja) | 1985-03-07 |
JPH034039Y2 JPH034039Y2 (en]) | 1991-02-01 |
Family
ID=30281557
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12332483U Granted JPS6033437U (ja) | 1983-08-10 | 1983-08-10 | リ−ド無しチップキャリヤ構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6033437U (en]) |
-
1983
- 1983-08-10 JP JP12332483U patent/JPS6033437U/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH034039Y2 (en]) | 1991-02-01 |
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